◆ logic1
1.소스
library ieee;
use ieee.std_logic_1164.all;
entity logic1 is
port(a,b,c :in bit;
y :out bit);
end logic1;
architecture sample of logic1 is
signal w, x : bit;
begin
no1: process(a,b)
begin
if (a= 1 ) or (b= 1 ) then w [= 1 ;
else w [= 0 ;
end if;
end process;
no2: process(b,c)
begin
if (b= 0 ) or (c= 0 ) then x [= 1 ;
else x [= 0 ;
end if;
end process;
no3: process(w,x)
begin
if (w=x) then y [= 0 ;
else y [= 1 ;
end if;
end process;
end sample;
2. 시뮬레이션
1) flow summary
2) wave form
3) time analyzer summary
3. 블록 다이어그램
1) 게이트
2) 블록
◆ over_write
library ieee;
use ieee.std_logic_1164.all;
entity over_write is
port ( a,b : in bit;
z : out bit);
end over_write;
architecture sample of over_write is
begin
process (a,b)
begin
z [= a and b;
z [= a or b;
end process;
end sample;
1. 소스
.... |
2014.01.20
26페이지
