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전체
(검색결과 약 21,270개 중 5페이지)
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| ◆ AND GATE(2 input)
1. 소스
library ieee;
use ieee.std_logic_1164.all;
entity andgate is
port(
sw1 : in std_logic;
sw2 : in std_logic;
led : out std_logic);
end andgate;
architecture sample of andgate is
begin
led [= sw1 and sw2;
end sample;
2. 시뮬레이션
1) Flow Summary
2) Waveform
3) time analyzer Summary
3. 블록다이어그램
※ 2입력 and 게이트의 정상적인 동작.. |
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| 경영정보시스템(MIS)에 대한 레포트
경영정보시스템
목차
경영정보시스템
I. 정보의 개념
1. 정보의 의의
2. 경영활동에서 정보의 중요성
3. 정보의 가치
1) 정확성
2) 신속성
3) 충분성
4) 관련성
II. 경영정보시스템의 의의와 필요성
1. 경영정보시스템의 의의
2. 경영정보시스템의 필요성
III. 경영정보시스템의 발전과정
1. 제1단계 : 단순한 자료처리(1950년~19
... 이하 생략 |
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| D/P PURCHASE CONTRACT
MESSRS.:
Buyer의 상호, 주소
Date
:
Contract No.
:
ABC Company, Ltd. as Buyer, hereby confirms having purchased from you as Seller, the following goods by the contract made on the above date and on the terms and conditions hereinafter set forth. Seller is hereby requested to sign and return the original and if any discrepancy be found by Sell.. |
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| PROFORMA INVOICE (견적송장) 작성 서식입니다.
Shipper/Exporter
No, Date of Invoice
For Account & Risk of Messurs
Remarks :
Notify Party
Port of Loading
Final Distination
Carrier
Sailing About
Marks and Numbers of PKGS
Description of Goods
Quantity/unit
Unit Price
Amount
Signed by:
TELEFAX :
TELEPHONE: |
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| South Korean strike hits economy
South Korea's government has warned the strike at its southern port of Pusan has cost the country $450m (£279m) in lost or delayed exports so far.
남쪽 부산항에서의 파업으로 한국은 수출지연과 손실로인해 지금까지 4억5천만달러 정도의 손실을 입었다라고 한국정부가 경고했다.
The Ministry of Commerce, Industry and Energy said the port was now runn.. |
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| Usance L/C PURCHASE CONTRACT
MESSRS.:
Buyer의 상호, 주소
Date
:
Contract No.
:
ABC Company, Ltd. as Buyer, hereby confirms having purchased from you as Seller, the
following goods by the contract made on the above date and on the terms and conditions
hereinafter set forth. Seller is hereby requested to sign and return the original and if any
discrepancy be fou.. |
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| D/A PURCHASE CONTRACT
MESSRS.:
Buyer의 상호, 주소
Date
:
Contract No.
:
ABC Company, Ltd. as Buyer, hereby confirms having purchased from you as Seller, the following goods by the contract made on the above date and on the terms and conditions hereinafter set forth. Seller is hereby requested to sign and return the original and if any discrepancy be found by Sell.. |
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| DD SALES CONTRACT
MESSRS.:
Buyer의 상호, 주소
Date
:
Contract No.
:
ABC Company, Ltd., as Seller, hereby confirms having sold to you as Buyer, the following
goods by this sales contract made on the above date and on the terms and conditions
hereinafter set forth. Buyer is hereby requested to sign and return the original and if any
discrepancy be found by Buyer.. |
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| 경영정보시스템(MIS)의 등장배경
... 자세한 내용은 본문 참고 |
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| 경영정보시스템(MIS)의 구성요소
... 자세한 내용은 본문 참고 |
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| 수입화물선취보증신청서입니다.
①선박회사명 (Shipping Co)
②송화인(Shipper)
③상업송장금액(Invoice Value)
④화물표시 및 번호 (Nos. & Marks)
⑤포장수(Packages)
⑥신용장(계약서)번호(Number of Credit)
⑦L/G번호(L/G Number)
⑧선하증권번호(Number of B/L)
⑨선박명(Vessel Name)
⑩도착(예정)일(Arrival Date)
⑪항해번호(Voyage No.)
⑫선적항 (Port of Loading)
⑬도착항 (Port of Discharge)
.. |
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| UDP 서버와 클라이언트 예제 소스입니다.
Port 지정과 데이타 전송횟수와 전송 성공율 및 실패율을 나타내어 줌니다.
UDP TEST용으로 제작 했고 VOIP기술 이용에 도움이 됨니다.
UDP 통신 모듈입니다.
2중 스레드와 2중 UDP 을 이용했습니다.
데이타을 지정한 횟수 많큼 보내서 회신하는 프로그램으로 UDP 전송율을 나타내주는 프로그램입니다.
프로그램은 VC++로 제작 했습니다. |
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| ○○○ CO., LTD
Address Cable :
Telex :
Tel :
Fax :
SALES CONTRACT
○○○ CO., LTD., as seller, hereby confirms having concluded the sales contract with you(your
company), as Buyer, to sell following goods on the date and on the terms and conditions herein-
after set forth. The Buyer is hereby requested to sign and return the original attached.
MESSRS
CONTRACT DATE
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| COMMERCIAL INVOICE
① Shipper/Exporter
⑧ No.& Date of Invoice
⑨ No.& date of L/C
⑩L/C issuing bank
② For Account & Risk of Messrs.
⑪ Remarks :
③ Notify Party
④ Port of loading
⑤ Final destination
⑥ Carrier
⑦ Sailing on or about
⑫ Marks and Numbers of PKGS
⑬ Description of goods
⑭ Quantity/Unit
⑮ Unit-price
Amount
P. O. Box : Signed by
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| ◆ logic1
1.소스
library ieee;
use ieee.std_logic_1164.all;
entity logic1 is
port(a,b,c :in bit;
y :out bit);
end logic1;
architecture sample of logic1 is
signal w, x : bit;
begin
no1: process(a,b)
begin
if (a= 1 ) or (b= 1 ) then w [= 1 ;
else w [= 0 ;
end if;
end process;
no2: process(b,c)
begin
if (b= 0 ) or (c= 0 ) then x [= 1 ;
else x [= 0 ;
end if;
end.. |
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