논리게이트 - VHDL 설계 언어 실습

◆ AND GATE(2 input)
1. 소스

library ieee;
use ieee.std_logic_1164.all;

entity andgate is
port(
sw1 : in std_logic;
sw2 : in std_logic;
led : out std_logic);
end andgate;

architecture sample of andgate is
begin
led [= sw1 and sw2;
end sample;

2. 시뮬레이션
1) Flow Summary

2) Waveform

3) time analyzer Summary

3. 블록다이어그램

※ 2입력 and 게이트의 정상적인 동작파형을 확인하였다.

◆ nor gate(2 input)
1. 소스

library ieee;
use ieee.std_logic_1164.all;

entity norgate is
port(a,b : in std_logic;
y : out std_logic);
end norgate;

architecture sample of norgate is
begin
y [= a nor b;
end sample;

2. 시뮬레이션
1) Flow Summary

2) Waveform

3) time analyzer Summary

3. 블록다이어그램

◆ nand_4
1.소스

library ieee;
use ieee.std_logic_1164.all;

entity nand_4 is
port( a,b,c,d : in std_logic;
y : out std_logic);
end nand_4;

architecture sample of nand_4 is
begin
y [= not(a and b and c and d);
end sample;

....

[hwp/pdf]논리게이트 - VHDL 설계 언어 실습